module top_led_uart( input wire clk, input wire rx, output wire tx, output reg [5:0] leds ); wire [7:0] data_out; wire valid; reg start_tx = 0; reg [7:0] data_in = 0; top_uart_rx_tx uart ( .clk(clk), .start(start_tx), .data_in(data_in), .rx(rx), .data_out(data_out), .valid(valid), .tx(tx) ); reg [1:0] state = 0; localparam IDLE = 2'd0; localparam TOGGLE = 2'd1; localparam SEND_BACK = 2'd2; always @(posedge clk) begin case (state) INIT: begin leds <= 6'b000000; start_tx <= 0; if (valid) begin leds <= data_out[5:0]; state <= SEND_BACK; end end IDLE: begin start_tx <= 0; if (valid) begin leds <= data_out[5:0]; state <= SEND_BACK; end end SEND_BACK: begin data_in <= data_out; start_tx <= 1; state <= TOGGLE; end TOGGLE: begin start_tx <= 0; state <= IDLE; end endcase end endmodule