`default_nettype none
module example1 (
    input wire clk,     // global clock
    input wire [7:0] edx,
    output reg strobe,   // output strobe
    output wire [7:0] res
);

localparam WIDTH=4;

reg[WIDTH-1:0] count = 0;

always_comb begin
  strobe = &count;
end

always_ff @(posedge clk) begin
   count <= count + 1;
end


assign res = edx + 5;

endmodule

/*
module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    
    always_comb 
        out = ~(in1 ^ in2) ^ in3;

endmodule
*/