#! :ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)"; :ivl_delay_selection "TYPICAL"; :vpi_time_precision - 12; :vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi"; :vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi"; :vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi"; :vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi"; :vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi"; S_000001de0ef7b970 .scope module, "tb_uart_rx" "tb_uart_rx" 2 3; .timescale -9 -12; P_000001de0f08dd40 .param/l "BAUD_RATE" 1 2 12, +C4<00000000000000011100001000000000>; P_000001de0f08dd78 .param/l "BIT_PERIOD" 1 2 13, +C4<00000000000000000000000011101010>; P_000001de0f08ddb0 .param/l "CLK_FREQ" 1 2 11, +C4<00000001100110111111110011000000>; P_000001de0f08dde8 .param/l "CLK_PERIOD_NS" 1 2 14, +C4<00000000000000000000000000100101>; v000001de0f0f5ab0_0 .var "clk", 0 0; v000001de0f0f6190_0 .net "data", 7 0, v000001de0f066a10_0; 1 drivers v000001de0f0f6230_0 .var/i "i", 31 0; v000001de0f0f62d0_0 .net "ready", 0 0, v000001de0f08f950_0; 1 drivers v000001de0f0f6410_0 .var "rx", 0 0; v000001de0f0f5fb0_0 .net "valid", 0 0, v000001de0f0f60f0_0; 1 drivers S_000001de0f08f630 .scope module, "rx_instance" "uart_rx" 2 19, 3 1 0, S_000001de0ef7b970; .timescale 0 0; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "rx"; .port_info 2 /OUTPUT 8 "data"; .port_info 3 /OUTPUT 1 "valid"; .port_info 4 /OUTPUT 1 "ready"; P_000001de0f08f7c0 .param/l "BAUD_RATE" 0 3 10, +C4<00000000000000011100001000000000>; P_000001de0f08f7f8 .param/l "BIT_PERIOD" 1 3 12, +C4<00000000000000000000000011101010>; P_000001de0f08f830 .param/l "CLK_FREQ" 0 3 9, +C4<00000001100110111111110011000000>; P_000001de0f08f868 .param/l "DATA" 1 3 16, C4<10>; P_000001de0f08f8a0 .param/l "IDLE" 1 3 14, C4<00>; P_000001de0f08f8d8 .param/l "START" 1 3 15, C4<01>; P_000001de0f08f910 .param/l "STOP" 1 3 17, C4<11>; v000001de0f066e60_0 .var "bit_index", 3 0; v000001de0ef7bb00_0 .net "clk", 0 0, v000001de0f0f5ab0_0; 1 drivers v000001de0ef7bf20_0 .var "clk_count", 15 0; v000001de0f066a10_0 .var "data", 7 0; v000001de0f08f950_0 .var "ready", 0 0; v000001de0f08f9f0_0 .net "rx", 0 0, v000001de0f0f6410_0; 1 drivers v000001de0f08de30_0 .var "rx_data", 7 0; v000001de0f0f5d30_0 .var "state", 1 0; v000001de0f0f60f0_0 .var "valid", 0 0; E_000001de0f08e270 .event posedge, v000001de0ef7bb00_0; S_000001de0f0a0300 .scope task, "send_bit" "send_bit" 2 29, 2 29 0, S_000001de0ef7b970; .timescale -9 -12; v000001de0f0f5a10_0 .var "b", 0 0; TD_tb_uart_rx.send_bit ; %load/vec4 v000001de0f0f5a10_0; %assign/vec4 v000001de0f0f6410_0, 0; %delay 8658000, 0; %end; S_000001de0f0a0490 .scope task, "send_byte" "send_byte" 2 38, 2 38 0, S_000001de0ef7b970; .timescale -9 -12; v000001de0f0f6370_0 .var "byte", 7 0; TD_tb_uart_rx.send_byte ; %pushi/vec4 0, 0, 1; %store/vec4 v000001de0f0f5a10_0, 0, 1; %fork TD_tb_uart_rx.send_bit, S_000001de0f0a0300; %join; %pushi/vec4 0, 0, 32; %store/vec4 v000001de0f0f6230_0, 0, 32; T_1.0 ; Top of for-loop %load/vec4 v000001de0f0f6230_0; %cmpi/s 8, 0, 32; %jmp/0xz T_1.1, 5; %load/vec4 v000001de0f0f6370_0; %load/vec4 v000001de0f0f6230_0; %part/s 1; %store/vec4 v000001de0f0f5a10_0, 0, 1; %fork TD_tb_uart_rx.send_bit, S_000001de0f0a0300; %join; T_1.2 ; for-loop step statement %load/vec4 v000001de0f0f6230_0; %addi 1, 0, 32; %store/vec4 v000001de0f0f6230_0, 0, 32; %jmp T_1.0; T_1.1 ; for-loop exit label %pushi/vec4 1, 0, 1; %store/vec4 v000001de0f0f5a10_0, 0, 1; %fork TD_tb_uart_rx.send_bit, S_000001de0f0a0300; %join; %delay 8658000, 0; %end; .scope S_000001de0f08f630; T_2 ; %pushi/vec4 0, 0, 1; %store/vec4 v000001de0f0f60f0_0, 0, 1; %pushi/vec4 1, 0, 1; %store/vec4 v000001de0f08f950_0, 0, 1; %pushi/vec4 0, 0, 2; %store/vec4 v000001de0f0f5d30_0, 0, 2; %pushi/vec4 0, 0, 8; %store/vec4 v000001de0f08de30_0, 0, 8; %end; .thread T_2; .scope S_000001de0f08f630; T_3 ; %wait E_000001de0f08e270; %load/vec4 v000001de0f0f5d30_0; %dup/vec4; %pushi/vec4 0, 0, 2; %cmp/u; %jmp/1 T_3.0, 6; %dup/vec4; %pushi/vec4 1, 0, 2; %cmp/u; %jmp/1 T_3.1, 6; %dup/vec4; %pushi/vec4 2, 0, 2; %cmp/u; %jmp/1 T_3.2, 6; %dup/vec4; %pushi/vec4 3, 0, 2; %cmp/u; %jmp/1 T_3.3, 6; %jmp T_3.4; T_3.0 ; %pushi/vec4 1, 0, 1; %assign/vec4 v000001de0f08f950_0, 0; %load/vec4 v000001de0f08f9f0_0; %nor/r; %flag_set/vec4 8; %jmp/0xz T_3.5, 8; %pushi/vec4 1, 0, 2; %assign/vec4 v000001de0f0f5d30_0, 0; %pushi/vec4 0, 0, 16; %assign/vec4 v000001de0ef7bf20_0, 0; %pushi/vec4 0, 0, 4; %assign/vec4 v000001de0f066e60_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v000001de0f0f60f0_0, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v000001de0f08f950_0, 0; T_3.5 ; %jmp T_3.4; T_3.1 ; %load/vec4 v000001de0ef7bf20_0; %pad/u 32; %cmpi/u 116, 0, 32; %jmp/0xz T_3.7, 5; %load/vec4 v000001de0ef7bf20_0; %addi 1, 0, 16; %assign/vec4 v000001de0ef7bf20_0, 0; %jmp T_3.8; T_3.7 ; %pushi/vec4 0, 0, 16; %assign/vec4 v000001de0ef7bf20_0, 0; %pushi/vec4 2, 0, 2; %assign/vec4 v000001de0f0f5d30_0, 0; T_3.8 ; %jmp T_3.4; T_3.2 ; %load/vec4 v000001de0ef7bf20_0; %pad/u 32; %cmpi/u 233, 0, 32; %jmp/0xz T_3.9, 5; %load/vec4 v000001de0ef7bf20_0; %addi 1, 0, 16; %assign/vec4 v000001de0ef7bf20_0, 0; %jmp T_3.10; T_3.9 ; %pushi/vec4 0, 0, 16; %assign/vec4 v000001de0ef7bf20_0, 0; %load/vec4 v000001de0f08f9f0_0; %ix/load 5, 0, 0; %ix/getv 4, v000001de0f066e60_0; %assign/vec4/off/d v000001de0f08de30_0, 4, 5; %load/vec4 v000001de0f066e60_0; %addi 1, 0, 4; %assign/vec4 v000001de0f066e60_0, 0; %load/vec4 v000001de0f066e60_0; %pad/u 32; %cmpi/e 7, 0, 32; %jmp/0xz T_3.11, 4; %pushi/vec4 3, 0, 2; %assign/vec4 v000001de0f0f5d30_0, 0; T_3.11 ; T_3.10 ; %jmp T_3.4; T_3.3 ; %load/vec4 v000001de0ef7bf20_0; %pad/u 32; %cmpi/u 233, 0, 32; %jmp/0xz T_3.13, 5; %load/vec4 v000001de0ef7bf20_0; %addi 1, 0, 16; %assign/vec4 v000001de0ef7bf20_0, 0; %jmp T_3.14; T_3.13 ; %pushi/vec4 0, 0, 2; %assign/vec4 v000001de0f0f5d30_0, 0; %load/vec4 v000001de0f08de30_0; %assign/vec4 v000001de0f066a10_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v000001de0f0f60f0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v000001de0f08f950_0, 0; T_3.14 ; %jmp T_3.4; T_3.4 ; %pop/vec4 1; %jmp T_3; .thread T_3; .scope S_000001de0ef7b970; T_4 ; %pushi/vec4 0, 0, 1; %store/vec4 v000001de0f0f5ab0_0, 0, 1; %pushi/vec4 1, 0, 1; %store/vec4 v000001de0f0f6410_0, 0, 1; %end; .thread T_4; .scope S_000001de0ef7b970; T_5 ; %delay 18000, 0; %load/vec4 v000001de0f0f5ab0_0; %inv; %store/vec4 v000001de0f0f5ab0_0, 0, 1; %jmp T_5; .thread T_5; .scope S_000001de0ef7b970; T_6 ; %vpi_call 2 50 "$display", "Start UART RX test" {0 0 0}; %delay 100000, 0; %pushi/vec4 85, 0, 8; %store/vec4 v000001de0f0f6370_0, 0, 8; %fork TD_tb_uart_rx.send_byte, S_000001de0f0a0490; %join; %delay 86580000, 0; %load/vec4 v000001de0f0f5fb0_0; %flag_set/vec4 9; %flag_get/vec4 9; %jmp/0 T_6.2, 9; %load/vec4 v000001de0f0f6190_0; %pushi/vec4 85, 0, 8; %cmp/e; %flag_get/vec4 4; %and; T_6.2; %flag_set/vec4 8; %jmp/0xz T_6.0, 8; %vpi_call 2 58 "$display", "Test ok : data = %b", v000001de0f0f6190_0 {0 0 0}; %jmp T_6.1; T_6.0 ; %vpi_call 2 60 "$display", "Test pas ok : data = %b, valid = %b", v000001de0f0f6190_0, v000001de0f0f5fb0_0 {0 0 0}; T_6.1 ; %vpi_call 2 62 "$finish" {0 0 0}; %end; .thread T_6; # The file index is used to find the file name in the following table. :file_names 4; "N/A"; ""; "tb_uart_rx.v"; "uart_rx.v";