#! :ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)"; :ivl_delay_selection "TYPICAL"; :vpi_time_precision - 12; :vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi"; :vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi"; :vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi"; :vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi"; :vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi"; S_00000175b6316720 .scope module, "tb_uart_tx" "tb_uart_tx" 2 3; .timescale -9 -12; v00000175b5febe70_0 .net "busy", 0 0, v00000175b5feb060_0; 1 drivers v00000175b5febf10_0 .var "clk", 0 0; v00000175b639b030_0 .var "data", 7 0; v00000175b63466a0_0 .var "start", 0 0; v00000175b6346a60_0 .net "tx", 0 0, v00000175b5febd30_0; 1 drivers E_00000175b5fead00 .event anyedge, v00000175b5feb060_0; S_00000175b63168b0 .scope module, "tx_instance" "uart_tx" 2 16, 3 1 0, S_00000175b6316720; .timescale 0 0; .port_info 0 /INPUT 1 "clk"; .port_info 1 /INPUT 1 "start"; .port_info 2 /INPUT 8 "data"; .port_info 3 /OUTPUT 1 "tx"; .port_info 4 /OUTPUT 1 "busy"; P_00000175b634db00 .param/l "BAUD_RATE" 0 3 10, +C4<00000000000000011100001000000000>; P_00000175b634db38 .param/l "BIT_PERIOD" 1 3 12, +C4<00000000000000000000000011101010>; P_00000175b634db70 .param/l "CLK_FREQ" 0 3 9, +C4<00000001100110111111110011000000>; v00000175b6316a40_0 .var "bit_index", 3 0; v00000175b5feb060_0 .var "busy", 0 0; v00000175b6316e60_0 .net "clk", 0 0, v00000175b5febf10_0; 1 drivers v00000175b5febb50_0 .var "clk_count", 15 0; v00000175b5febbf0_0 .net "data", 7 0, v00000175b639b030_0; 1 drivers v00000175b5febc90_0 .net "start", 0 0, v00000175b63466a0_0; 1 drivers v00000175b5febd30_0 .var "tx", 0 0; v00000175b5febdd0_0 .var "tx_data", 7 0; E_00000175b5fea980 .event posedge, v00000175b6316e60_0; .scope S_00000175b63168b0; T_0 ; %pushi/vec4 0, 0, 8; %store/vec4 v00000175b5febdd0_0, 0, 8; %end; .thread T_0; .scope S_00000175b63168b0; T_1 ; %pushi/vec4 1, 0, 1; %store/vec4 v00000175b5febd30_0, 0, 1; %pushi/vec4 0, 0, 1; %store/vec4 v00000175b5feb060_0, 0, 1; %end; .thread T_1; .scope S_00000175b63168b0; T_2 ; %wait E_00000175b5fea980; %load/vec4 v00000175b5febc90_0; %flag_set/vec4 9; %flag_get/vec4 9; %jmp/0 T_2.2, 9; %load/vec4 v00000175b5feb060_0; %nor/r; %and; T_2.2; %flag_set/vec4 8; %jmp/0xz T_2.0, 8; %pushi/vec4 1, 0, 1; %assign/vec4 v00000175b5feb060_0, 0; %pushi/vec4 0, 0, 4; %assign/vec4 v00000175b6316a40_0, 0; %pushi/vec4 0, 0, 16; %assign/vec4 v00000175b5febb50_0, 0; %load/vec4 v00000175b5febbf0_0; %assign/vec4 v00000175b5febdd0_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v00000175b5febd30_0, 0; %jmp T_2.1; T_2.0 ; %load/vec4 v00000175b5feb060_0; %flag_set/vec4 8; %jmp/0xz T_2.3, 8; %load/vec4 v00000175b5febb50_0; %pad/u 32; %cmpi/u 233, 0, 32; %jmp/0xz T_2.5, 5; %load/vec4 v00000175b5febb50_0; %addi 1, 0, 16; %assign/vec4 v00000175b5febb50_0, 0; %jmp T_2.6; T_2.5 ; %pushi/vec4 0, 0, 16; %assign/vec4 v00000175b5febb50_0, 0; %load/vec4 v00000175b6316a40_0; %pad/u 32; %cmpi/e 0, 0, 32; %jmp/0xz T_2.7, 4; %pushi/vec4 0, 0, 1; %assign/vec4 v00000175b5febd30_0, 0; %jmp T_2.8; T_2.7 ; %load/vec4 v00000175b6316a40_0; %pad/u 32; %cmpi/u 9, 0, 32; %jmp/0xz T_2.9, 5; %load/vec4 v00000175b5febdd0_0; %load/vec4 v00000175b6316a40_0; %pad/u 32; %subi 1, 0, 32; %part/u 1; %assign/vec4 v00000175b5febd30_0, 0; %jmp T_2.10; T_2.9 ; %load/vec4 v00000175b6316a40_0; %pad/u 32; %cmpi/e 9, 0, 32; %jmp/0xz T_2.11, 4; %pushi/vec4 1, 0, 1; %assign/vec4 v00000175b5febd30_0, 0; %jmp T_2.12; T_2.11 ; %pushi/vec4 0, 0, 1; %assign/vec4 v00000175b5feb060_0, 0; T_2.12 ; T_2.10 ; T_2.8 ; %load/vec4 v00000175b6316a40_0; %addi 1, 0, 4; %assign/vec4 v00000175b6316a40_0, 0; T_2.6 ; %jmp T_2.4; T_2.3 ; %pushi/vec4 1, 0, 1; %assign/vec4 v00000175b5febd30_0, 0; T_2.4 ; T_2.1 ; %jmp T_2; .thread T_2; .scope S_00000175b6316720; T_3 ; %pushi/vec4 0, 0, 1; %store/vec4 v00000175b5febf10_0, 0, 1; %pushi/vec4 0, 0, 1; %store/vec4 v00000175b63466a0_0, 0, 1; %pushi/vec4 0, 0, 8; %store/vec4 v00000175b639b030_0, 0, 8; %end; .thread T_3; .scope S_00000175b6316720; T_4 ; %delay 18500, 0; %load/vec4 v00000175b5febf10_0; %inv; %store/vec4 v00000175b5febf10_0, 0, 1; %jmp T_4; .thread T_4; .scope S_00000175b6316720; T_5 ; %vpi_call 2 25 "$dumpfile", "uart_tx.vcd" {0 0 0}; %vpi_call 2 26 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000175b6316720 {0 0 0}; %delay 100000, 0; %pushi/vec4 165, 0, 8; %assign/vec4 v00000175b639b030_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v00000175b63466a0_0, 0; %delay 37000, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v00000175b63466a0_0, 0; T_5.0 ; %load/vec4 v00000175b5febe70_0; %pad/u 32; %pushi/vec4 0, 0, 32; %cmp/e; %flag_get/vec4 4; %cmpi/ne 1, 0, 1; %jmp/0xz T_5.1, 6; %wait E_00000175b5fead00; %jmp T_5.0; T_5.1 ; %delay 1000000, 0; %pushi/vec4 60, 0, 8; %assign/vec4 v00000175b639b030_0, 0; %pushi/vec4 1, 0, 1; %assign/vec4 v00000175b63466a0_0, 0; %delay 37000, 0; %pushi/vec4 0, 0, 1; %assign/vec4 v00000175b63466a0_0, 0; T_5.2 ; %load/vec4 v00000175b5febe70_0; %pad/u 32; %pushi/vec4 0, 0, 32; %cmp/e; %flag_get/vec4 4; %cmpi/ne 1, 0, 1; %jmp/0xz T_5.3, 6; %wait E_00000175b5fead00; %jmp T_5.2; T_5.3 ; %delay 1000000, 0; %vpi_call 2 46 "$stop" {0 0 0}; %end; .thread T_5; # The file index is used to find the file name in the following table. :file_names 4; "N/A"; ""; "tb_uart_tx.v"; "uart_tx_old.v";