`default_nettype none
module top_uart_loopback (
    input wire clk, // 27 MHz
    input wire rx,
    output wire tx,
    output wire [5:0] leds
);

    wire rx_received;
    wire [7:0] rx_data;
    reg [7:0] tx_data;
    reg tx_enable;
    reg rx_enable;

    wire tx_ready;

/*     // === UART RX ===
     uart_rx uart_rx_inst (
         .clk(clk),
         .rst_p(1'b0),
         .rx_pin(rx),
        .rx_received(tx_enable),
         .rx_received(rx_received),
         .rx_enable(1'b1),
		.rx_enable(tx_ready),
         //.rx_data(rx_data)
 		.rx_data(rx_data)
     );*/

     rxuartlite uart_rx_inst (
        .i_clk(clk),
        .i_reset(1'b0),
        .i_uart_rx(rx),
        .o_wr(rx_received),
        .o_data(rx_data)
    );

reg [7:0] stored_data;

reg [7:0] data_const = 8'h31;
//initial data_const = ;

wire r;

    // === UART TX ===
    uart_tx uart_tx_inst (
        .clk(clk),
        .rst_p(1'b0),
        .data(tx_data),
        .tx_enable(tx_enable),
        .tx_ready(tx_ready),
        .tx(tx)
    );

    /* other_uart_tx uart_tx_inst (
         .clk(clk),
         .rst_n(1'b1),
         .tx_data(data_const),
         .tx_data_valid(tx_enable),
         .tx_data_ready(tx_ready),
         .tx_pin(tx)
     );*/


/* reg delay_active = 0;
 reg [31:0] delay_counter = 0;
 localparam DELAY_CYCLES = 27000000 / 2; // 0.5 second delay at 27 MHz
 reg data_ready = 0;


     // Store received data and trigger delay
     always @(posedge clk) begin

         begin
             // Capture new received data
             if (rx_received && !data_ready) begin
                 stored_data <= rx_data;
                 data_ready <= 1'b1;
                 delay_active <= 1'b1;
                 delay_counter <= DELAY_CYCLES;
             end

             // Countdown delay
             if (delay_active) begin
                 if (delay_counter > 0) begin
                     delay_counter <= delay_counter - 1;
                 end
                 else begin
                     delay_active <= 1'b0;
                 end
             end
         end
     end

     // Control transmission
     always @(posedge clk) begin

         begin
             tx_enable <= 1'b0;  // Default assignment
            
             // Start transmission when delay completes and UART is ready
            if (data_ready && !delay_active && tx_ready && !tx_enable) begin
                 tx_enable <= 1'b1;
                 data_ready <= 1'b0;  // Clear flag after starting transmission
             end
         end
     end  */  


localparam CLK_FREQ = 27_000_000; // 27 MHz
localparam DATA_BYTE = 8'h31; // ASCII '1'

  // State machine to continuously send the byte
    reg [31:0] delay_counter;
    localparam DELAY_CYCLES = CLK_FREQ / 2; // 0.5 second delay between transmissions
    
    always @(posedge clk) begin
        begin
            // Default assignments
            tx_enable <= 1'b0;
            
            if (tx_ready && delay_counter == 0) begin
                // Start new transmission
                tx_enable <= 1'b1;
                data_const <= DATA_BYTE;
                tx_data <= rx_data; 

                //leds[5:0] <= rx_data[5:0]; // Display received data on LEDs
                leds[5] <= rx_received;
                delay_counter <= DELAY_CYCLES;
            end
            else if (delay_counter > 0) begin
                // Count down delay
                delay_counter <= delay_counter - 1;
            end
        end
    end




/*
    // === FSM avec délai ===
    localparam IDLE = 0, WAIT = 1, SEND = 2;
    reg [1:0] state = IDLE;
    reg [8:0] delay_counter = 0; 

    always @(posedge clk) begin
        leds[5] <= rx;
        leds[4] <= tx;

        case (state)
            IDLE: begin
                tx_enable <= 0;
                delay_counter <= 0;

                if (rx_received && tx_ready) begin
                    tx_data <= rx_data;
                    state <= WAIT;
                    leds[0] <= 0; 
                    leds[1] <= 1; 
                end
            end

            WAIT: begin
                delay_counter <= delay_counter + 1;

                if (delay_counter == 8'd400 && tx_ready) begin 
                    tx_enable <= 1;
                    state <= SEND;
                end else begin
                    tx_enable <= 0;
                end

                leds[0] <= 1;
                leds[1] <= 0;
            end


            SEND: begin
                tx_enable <= 0;
                state <= IDLE;

                leds[0] <= 0;
                leds[1] <= 0; // Envoi terminé
            end
        endcase
    end
*/
endmodule