@echo off
rem https://github.com/YosysHQ/apicula

set file_name=src\verilog\counter.v src\verilog\blink.v src\verilog\blink_top.v
set constraints_file=constraints\blink_led.cst

yosys -p "read_verilog -sv %file_name%; synth_gowin -json runs\blink_led_c.json"

set DEVICE=GW2AR-LV18QN88C8/I7
set BOARD=tangnano20k

nextpnr-himbaechel --json runs\blink_led_c.json --write runs\pnr_blink_led.json --device %DEVICE% --vopt cst=%constraints_file% --vopt family=GW2A-18C

gowin_pack -d %DEVICE% -o runs\blink_led_c.fs runs\pnr_blink_led.json

rem openfpgaloader -b %BOARD% blink_led_c.fs