forked from tanchou/Verilog
Louis TANCHOU
54bf6df85b
- Implemented a FIFO buffer in Verilog for data storage. - Created a simplified UART transmitter (txuartlite) for serial communication. - Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow. - Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission. - Added a testbench (tb_dht11) for simulating the DHT11 module functionality. - Updated README with project description and command references. - Created build and simulation scripts for both Linux and Windows environments. - Added constraints file for hardware configuration. - Implemented a state machine for managing measurement and data transmission.
25 lines
382 B
Bash
Executable File
25 lines
382 B
Bash
Executable File
#!/bin/bash
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# Charger l'environnement OSS CAD Suite
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source /home/louis/oss-cad-suite/environment
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mkdir -p runs
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case "$1" in
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sim)
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bash scripts/linux/simulate.sh
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;;
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wave)
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bash scripts/linux/gtkwave.sh
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;;
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clean)
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bash scripts/linux/clean.sh
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;;
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build)
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bash scripts/linux/build.sh
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;;
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*)
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echo "Usage: $0 {sim|wave|clean|build}"
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;;
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esac
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