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Verilog_Louis
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004def5ba28610c8ddb7e15b3914bcfd911dfe4c
Verilog_Louis
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Semaine_4
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Gamenight77
004def5ba2
Add README for UART loopback issue and delay explanation
2025-05-09 11:58:55 +02:00
..
FIFO
MAJ FIFO -> turn wire rd_data into register
2025-05-09 10:27:13 +02:00
UART
MAJ FIFO -> turn wire rd_data into register
2025-05-09 10:27:13 +02:00
UART_FIFO
Add README for UART loopback issue and delay explanation
2025-05-09 11:58:55 +02:00
UART_ULTRASON
Add WAIT state to FSM and implement delay mechanism in UART module
2025-05-07 18:07:45 +02:00