forked from tanchou/Verilog
96 lines
1.3 KiB
Verilog
96 lines
1.3 KiB
Verilog
`timescale 1ns/1ps
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module tb_fifo;
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reg clk = 0;
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reg wr_en = 0;
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reg rd_en = 0;
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reg [7:0] wr_data = 0;
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wire [7:0] rd_data;
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wire full;
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wire empty;
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always #18.5 clk = ~clk;
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fifo #(
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.DETPH(16),
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.WIDTH(8)
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) fifo_inst (
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.clk(clk),
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.wr_en(wr_en),
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.wr_data(wr_data),
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.rd_en(rd_en),
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.rd_data(rd_data),
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.full(full),
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.empty(empty)
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);
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initial begin
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$dumpfile("runs/fifo.vcd");
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$dumpvars(0, tb_fifo);
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wr_en = 1;
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wr_data = 8'hAA;
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#37.0;
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wr_en = 0;
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#37.0;
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wr_en = 1;
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wr_data = 8'hBB;
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#37.0;
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wr_en = 0;
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#37.0;
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wr_en = 1;
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wr_data = 8'hCC;
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#37.0;
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wr_en = 0;
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#37.0;
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$display("rd_data: %h", rd_data);
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rd_en = 1;
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$display("rd_data: %h", rd_data);
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#37.0;
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rd_en = 0;
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#37.0;
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rd_en = 1;
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$display("rd_data: %h", rd_data);
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#37.0;
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rd_en = 0;
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#37.0;
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rd_en = 1;
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$display("rd_data: %h", rd_data);
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#37.0;
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rd_en = 0;
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#37.0;
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rd_en = 1;
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$display("rd_data: %h", rd_data);
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#19.0;
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rd_en = 0;
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#37.0;
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$finish;
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end
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endmodule |