forked from tanchou/Verilog
861c9869f5
- Created DHT11 interface in Verilog to handle communication with DHT11 sensor. - Implemented LED control logic to indicate sensor status and data readiness. - Added project scripts for building, cleaning, and simulating the design. - Established constraints for FPGA pin assignments. - Developed testbench for DHT11 UART communication. - Updated README files to reflect project functionality and commands.
211 lines
6.8 KiB
Verilog
211 lines
6.8 KiB
Verilog
module dht11_interface (
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input wire i_clk, // 27 MHz
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inout wire io_dht11_sig,
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input wire i_start,
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output reg o_dht11_data_ready,
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output reg o_busy,
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output wire [7:0] o_temp_data,
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output wire [7:0] o_hum_data,
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output reg o_dht11_error
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);
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// === DHT11 INTERFACE ===
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// === PARAMÈTRES ===
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parameter CLK_FREQ = 27_000_000;
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localparam T_18MS = CLK_FREQ * 18 / 1000; // cycles pour 18ms
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localparam T_80US = CLK_FREQ * 81 / 1_000_000;
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localparam T_79US = CLK_FREQ * 79 / 1_000_000;
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localparam T_71US = CLK_FREQ * 71 / 1_000_000;
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localparam T_51US = CLK_FREQ * 51 / 1_000_000;
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localparam T_50US = CLK_FREQ * 50 / 1_000_000;
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localparam T_49US = CLK_FREQ * 49 / 1_000_000;
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localparam T_40US = CLK_FREQ * 40 / 1_000_000;
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localparam T_28US = CLK_FREQ * 28 / 1_000_000;
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localparam T_20US = CLK_FREQ * 20 / 1_000_000;
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// === Signal bidirectionnel ===
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reg sig_dir;
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reg sig_out;
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wire sig_in;
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assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz)
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assign sig_in = io_dht11_sig;
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// === REGISTRES ===
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reg [3:0] state;
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reg [31:0] timer;
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reg [7:0] temp_data, hum_data;
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reg [7:0] temp_dec, hum_dec, checksum;
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reg [2:0] bit_count;
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reg [5:0] bit_index;
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reg [39:0] raw_data;
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// === INITIALISATION ===
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initial begin
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sig_dir = 0;
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sig_out = 1;
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timer = 0;
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state = IDLE;
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bit_index = 0;
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raw_data = 0;
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o_dht11_data_ready = 0;
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o_dht11_error = 0;
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end
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// === FSM ===
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localparam IDLE = 4'd0, // Pull up la ligne
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START = 4'd1, // Pull low 18ms
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WAIT_RESPONSE = 4'd2, // Release la ligne (entre 20 et 40us)
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RESPONSE_LOW = 4'd3, // DHT11 pull low 80us
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RESPONSE_HIGH = 4'd4, // DHT11 pull high 80us
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READ_READ_BITS_LOW = 4'd5,
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READ_READ_BITS_HIGH = 4'd6,
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DONE = 4'd7,
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ERROR = 4'd8;
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// === FSM principale ===
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always @(posedge i_clk) begin
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case (state)
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IDLE: begin
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sig_dir <= 0;
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sig_out <= 1;
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timer <= 0;
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bit_index <= 0;
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raw_data <= 0;
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o_busy <= 0;
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if (i_start) begin
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sig_dir <= 1;
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sig_out <= 0;
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timer <= 0;
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o_busy <= 1;
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state <= START;
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o_dht11_data_ready <= 0;
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o_dht11_error <= 0;
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end
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end
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START: begin
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timer <= timer + 1;
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if (timer >= T_18MS) begin
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sig_dir <= 0; // libérer la ligne
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timer <= 0;
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state <= WAIT_RESPONSE;
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end
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end
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WAIT_RESPONSE: begin
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timer <= timer + 1;
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if (sig_in == 0) begin
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if (timer > T_20US && timer < T_40US) begin
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timer <= 0;
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state <= RESPONSE_LOW;
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end else begin
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state <= ERROR;
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end
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end else if (timer > T_40US) begin
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state <= ERROR;
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end
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end
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RESPONSE_LOW: begin
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timer <= timer + 1;
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if (sig_in == 1) begin
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if (timer > T_79US && timer < T_80US) begin
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timer <= 0;
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state <= RESPONSE_HIGH;
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end else begin
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state <= ERROR;
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end
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end else if (timer > T_80US) begin
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state <= ERROR;
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end
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end
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RESPONSE_HIGH: begin
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timer <= timer + 1;
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if (sig_in == 0) begin
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if (timer > T_79US && timer < T_80US) begin
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timer <= 0;
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state <= READ_BITS_LOW;
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end else begin
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state <= ERROR;
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end
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end else if (timer > T_80US) begin
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state <= ERROR;
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end
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end
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READ_BITS_LOW: begin
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timer <= timer + 1;
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if (sig_in == 1) begin
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if (timer > T_49US && timer < T_51US) begin
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timer <= 0;
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state <= READ_BITS_HIGH;
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end else begin
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state <= ERROR;
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end
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end else if (timer > T_28US) begin
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state <= ERROR;
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end
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end
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READ_BITS_HIGH: begin // entre 26 et 28us = 0 et ~70us = 1
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timer <= timer + 1;
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if (sig_in == 0) begin
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if (timer < T_26US) begin
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state <= ERROR;
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end
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raw_data <= {raw_data[38:0], (timer > T_28US)}; // 1 si high > ~28us
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timer <= 0;
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bit_index <= bit_index + 1;
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if (bit_index == 39) begin // Code a testé ici pour etre sur de capter le dernier bit
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state <= DONE;
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end else begin
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state <= READ_BITS_LOW;
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end
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end else if (timer > T_71US) begin
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state <= ERROR;
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end
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end
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DONE: begin
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hum_data <= raw_data[39:32];
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hum_dec <= raw_data[31:24];
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temp_data <= raw_data[23:16];
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temp_dec <= raw_data[15:8];
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checksum <= raw_data[7:0];
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if (checksum == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin
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o_hum_data <= raw_data[39:32];
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o_temp_data <= raw_data[23:16];
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o_dht11_data_ready <= 1;
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end else begin
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o_dht11_error <= 1;
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end
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o_busy <= 0;
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state <= IDLE;
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end
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ERROR: begin
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o_dht11_error <= 1;
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state <= IDLE;
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end
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endcase
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end
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endmodule
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