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Verilog_Louis
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0f14bf24a6cc7056c38980daff8490191e21f574
Verilog_Louis
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Semaine_7
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ESP32
/
leds_commands
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tests
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Gamenight77
12ce0d38a7
Update UART baud rate to 1,000,000 in ESP32 and FPGA modules; adjust example command in connectESP.py
2025-05-28 14:47:38 +02:00
..
pyhton
Update UART baud rate to 1,000,000 in ESP32 and FPGA modules; adjust example command in connectESP.py
2025-05-28 14:47:38 +02:00
verilog
Code FPGA fonctionnel
2025-05-27 15:36:40 +02:00