forked from tanchou/Verilog
74 lines
1.7 KiB
Verilog
74 lines
1.7 KiB
Verilog
module top_ultrason_uart(
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input wire clk,
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input wire start,
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inout wire sig,
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output wire tx
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);
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parameter CLK_FREQ = 27_000_000;
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parameter BAUD_RATE = 115_200;
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localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
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// Paramètres pour le capteur à ultrasons
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wire [15:0] distance;
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wire [2:0] state_sensor;
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// Signaux pour l'UART TX
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reg [15:0] tx_data;
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reg tx_start = 0;
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// Instance du capteur à ultrasons
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ultrasonic_fpga #(
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.CLK_FREQ(CLK_FREQ)
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) sensor_inst (
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.clk(clk),
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.start(start),
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.sig(sig),
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.distance(distance),
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.state(state_sensor)
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);
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// Instance de l'UART TX
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uart_tx #(
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.CLK_FREQ(CLK_FREQ),
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.BAUD_RATE(BAUD_RATE)
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) tx_instance (
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.clk(clk),
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.start(tx_start),
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.data(tx_data[7:0]),
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.tx(tx)
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);
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reg [31:0] wait_counter;
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reg [1:0] state;
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localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
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localparam START = 2'd0;
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localparam WAIT = 2'd1;
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always @(posedge clk) begin
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case(state)
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START:begin
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if (state_sensor == 3'd6) begin // Lorsque la mesure est terminée, préparer les données
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tx_data <= distance;
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tx_start <= 1;
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state <= WAIT;
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end
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end
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WAIT:begin
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tx_start <= 0;
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wait_counter <= wait_counter + 1;
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if (wait_counter >= WAIT_NEXT_CYCLES) begin
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state <= START;
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wait_counter <= 0;
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end
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end
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endcase
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end
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endmodule |