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Verilog_Louis
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12ce0d38a7bda0c3ffdd6d4cab81f3f1af1c13f6
Verilog_Louis
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Semaine_7
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Gamenight77
12ce0d38a7
Update UART baud rate to 1,000,000 in ESP32 and FPGA modules; adjust example command in connectESP.py
2025-05-28 14:47:38 +02:00
..
DHT11
Refactor DHT11 interface to support 16-bit temperature and humidity data, update checksum handling, and improve state machine logic
2025-05-27 13:34:59 +02:00
DHT11_UART
Code FPGA fonctionnel
2025-05-27 15:36:40 +02:00
ESP32
Update UART baud rate to 1,000,000 in ESP32 and FPGA modules; adjust example command in connectESP.py
2025-05-28 14:47:38 +02:00