forked from tanchou/Verilog
151 lines
4.4 KiB
Verilog
151 lines
4.4 KiB
Verilog
module ultrasonic_fpga #(
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parameter integer CLK_FREQ = 27_000_000 // Fréquence d'horloge en Hz
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)(
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input wire clk,
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input wire start,
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inout wire sig, // Broche bidirectionnelle vers le capteur
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output reg [15:0] distance, // Distance mesurée en cm
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output reg busy,
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output reg done
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);
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reg [15:0] trig_counter = 0;
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reg [31:0] echo_counter = 0;
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reg [31:0] echo_div_counter = 0;
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reg [15:0] distance_counter = 0;
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reg sig_out;
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reg sig_dir; // 1: output, 0: input
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assign sig = sig_dir ? sig_out : 1'bz; // bz pour dire que le fpga laisse le fils libre et n'oblige pas de valeur
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reg sig_int, sig_ok;
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reg [2:0] state = IDLE;
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localparam IDLE = 3'd0,
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TRIG_HIGH = 3'd1,
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TRIG_LOW = 3'd2,
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WAIT_ECHO = 3'd3,
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MEASURE_ECHO = 3'd4,
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COMPUTE = 3'd5,
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DONE = 3'd6,
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WAIT_NEXT = 3'd7;
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localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
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localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
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localparam integer MAX_CM = 350;
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localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1000000;
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localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
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reg [31:0] wait_counter;
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always @(posedge clk) begin
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sig_int <= sig;
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sig_ok <= sig_int;
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end
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always @(posedge clk) begin
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busy <= (state != IDLE);
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end
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always @(posedge clk) begin // FSM
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case (state)
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IDLE: begin
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done <= 1;
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sig_out <= 0;
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sig_dir <= 0;
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distance <= 0;
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if (start) begin
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state <= TRIG_HIGH;
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trig_counter <= 0;
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done <= 0;
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end
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end
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TRIG_HIGH: begin
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sig_out <= 1;
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sig_dir <= 1;
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if (trig_counter < TRIG_PULSE_CYCLES) begin
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trig_counter <= trig_counter + 1;
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end else begin
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trig_counter <= 0;
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state <= TRIG_LOW;
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end
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end
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TRIG_LOW: begin
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sig_out <= 0;
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sig_dir <= 0; // Mettre en entrée
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if (sig_ok) begin
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state <= TRIG_LOW;
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end else
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state <= WAIT_ECHO;
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end
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WAIT_ECHO: begin
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if (sig_ok) begin
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echo_counter <= 0;
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state <= MEASURE_ECHO;
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end else if (echo_counter >= TIMEOUT_CYCLES) begin
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distance <= 0;
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state <= DONE;
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end else begin
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echo_counter <= echo_counter + 1;
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end
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end
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MEASURE_ECHO: begin
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if (sig_ok) begin
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if (echo_counter < TIMEOUT_CYCLES) begin
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echo_counter <= echo_counter + 1;
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end else begin
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state <= DONE;
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end
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end else begin
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state <= COMPUTE;
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end
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end
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COMPUTE: begin
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if (echo_counter >= DIST_DIVISOR) begin
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echo_counter <= echo_counter - DIST_DIVISOR;
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distance_counter <= distance_counter + 1;
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state <= COMPUTE;
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end else begin
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distance <= distance_counter;
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state <= DONE;
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end
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end
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DONE: begin
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if (start) begin
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wait_counter <= 0;
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state <= WAIT_NEXT;
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end else begin
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state <= IDLE;
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end
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done <= 1;
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end
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WAIT_NEXT: begin
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wait_counter <= wait_counter + 1;
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if (wait_counter >= WAIT_NEXT_CYCLES) begin
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state <= TRIG_HIGH;
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trig_counter <= 0;
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distance_counter <= 0;
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echo_counter <= 0;
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end
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end
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default: begin
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state <= IDLE; // Reset to IDLE state in case of an error
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end
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endcase
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end
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endmodule |