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verlan
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Verilog_Louis
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tanchou/Verilog
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1d6677d67d4ffd61c56c54bd6ad7a230f47231ea
Verilog_Louis
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Semaine_4
/
FIFO
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Gamenight77
b7d184d02f
Gros patch sur la fifo et rx fifo pour gagner des tick d'horloge, uart comand fonctionne toujours pas
2025-05-13 10:21:28 +02:00
..
constraints
Add UART TX module and testbench, update scripts and constraints
2025-05-05 15:23:44 +02:00
scripts
Tb for fifo working fine
2025-05-06 09:14:59 +02:00
src
/verilog
Gros patch sur la fifo et rx fifo pour gagner des tick d'horloge, uart comand fonctionne toujours pas
2025-05-13 10:21:28 +02:00
tests
/verilog
Tb for fifo working fine
2025-05-06 09:14:59 +02:00
.gitignore
Add UART TX module and testbench, update scripts and constraints
2025-05-05 15:23:44 +02:00
project.bat
Add UART TX module and testbench, update scripts and constraints
2025-05-05 15:23:44 +02:00
