forked from tanchou/Verilog
119 lines
2.7 KiB
Verilog
119 lines
2.7 KiB
Verilog
module uart_top(
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input clk,
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input rst,
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input uart_rx,
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output uart_tx
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);
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parameter CLK_FRE = 27_000_000; // Mhz
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parameter UART_FRE = 115200; // Baud
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localparam IDLE = 0;
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localparam SEND = 1; // send
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localparam WAIT = 2; // wait 1 second and send uart received data
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reg[7:0] tx_data;
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reg[7:0] tx_str;
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reg tx_data_valid;
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wire tx_data_ready;
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reg[7:0] tx_cnt;
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wire[7:0] rx_data;
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wire rx_data_valid;
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wire rx_data_ready;
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reg[31:0] wait_cnt;
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reg[3:0] state;
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wire rst_p = rst;
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assign rx_data_ready = 1'b1; //always can receive data,
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always@(posedge clk or negedge rst_p)
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begin
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if(rst_p == 1'b1)
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begin
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wait_cnt <= 32'd0;
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tx_data <= 8'd0;
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state <= IDLE;
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tx_cnt <= 8'd0;
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tx_data_valid <= 1'b0;
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end
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else
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case(state)
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IDLE:begin
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state <= SEND;
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end
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SEND:begin
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wait_cnt <= 32'd0;
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tx_data <= tx_str;
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if(tx_data_valid == 1'b1 && tx_data_ready == 1'b1 && tx_cnt < DATA_NUM - 1)//Send 12 bytes data
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begin
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tx_cnt <= tx_cnt + 8'd1; //Send data counter
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end
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else if(tx_data_valid && tx_data_ready)//last byte sent is complete
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begin
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tx_cnt <= 8'd0;
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tx_data_valid <= 1'b0;
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state <= WAIT;
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end
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else if(~tx_data_valid)
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begin
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tx_data_valid <= 1'b1;
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end
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end
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WAIT:begin
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wait_cnt <= wait_cnt + 32'd1;
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if(rx_data_valid == 1'b1)
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begin
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tx_data_valid <= 1'b1;
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tx_data <= rx_data; // send uart received data
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end
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else if(tx_data_valid && tx_data_ready)
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begin
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tx_data_valid <= 1'b0;
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end
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else if(wait_cnt >= CLK_FRE * 1000_000) // wait for 1 second
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state <= SEND;
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end
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default:
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state <= IDLE;
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endcase
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end
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always@(*)
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tx_str <= send_data[(DATA_NUM - 1 - tx_cnt) * 8 +: 8];
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uart_rx#
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(
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.CLK_FRE(CLK_FRE),
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.BAUD_RATE(UART_FRE)
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) uart_rx_inst
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(
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.clk (clk),
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.rst_p (rst_p),
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.rx_data (rx_data),
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.rx_data_valid (rx_data_valid),
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.rx_data_ready (rx_data_ready),
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.rx_pin (uart_rx)
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);
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uart_tx#
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(
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.CLK_FRE(CLK_FRE),
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.BAUD_RATE(UART_FRE)
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) uart_tx_inst
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(
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.clk (clk),
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.rst_p (rst_p),
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.tx_data (tx_data),
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.tx_data_valid (tx_data_valid),
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.tx_data_ready (tx_data_ready),
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.tx_pin (uart_tx)
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);
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endmodule |