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Verilog_Louis
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3f3e4fcd6bcca3d609a9ed03a88d727e53d7a5d0
Verilog_Louis
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Semaine_7
/
ESP32
/
leds_commands
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Gamenight77
3f3e4fcd6b
Update clock frequency in fpga_wifi_led module to 57.857142 MHz
2025-05-29 13:25:53 +02:00
..
constraints
Update FPGA constraints and reintroduce WiFi functionality with touch sensor reset handling
2025-05-27 18:45:09 +02:00
IP
/verilog
Code FPGA fonctionnel
2025-05-27 15:36:40 +02:00
scripts
Code FPGA fonctionnel
2025-05-27 15:36:40 +02:00
src
Update clock frequency in fpga_wifi_led module to 57.857142 MHz
2025-05-29 13:25:53 +02:00
tests
Update UART baud rate to 1,000,000 in ESP32 and FPGA modules; adjust example command in connectESP.py
2025-05-28 14:47:38 +02:00
.gitignore
Code FPGA fonctionnel
2025-05-27 15:36:40 +02:00
project.bat
Code FPGA fonctionnel
2025-05-27 15:36:40 +02:00
project.sh
Code FPGA fonctionnel
2025-05-27 15:36:40 +02:00