forked from tanchou/Verilog
48 lines
1.2 KiB
Verilog
48 lines
1.2 KiB
Verilog
module uart_top(
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input wire clk,
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input wire rst,
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input wire uart_rx,
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output wire uart_tx,
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// Interfaces RX
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output wire [7:0] rx_data,
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output wire rx_data_valid,
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input wire rx_data_ready,
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// Interfaces TX
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input wire [7:0] tx_data,
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input wire tx_data_valid,
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output wire tx_data_ready
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);
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parameter CLK_FRE = 27_000_000; // Hz
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parameter UART_FRE = 115200; // Baudrate
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// === Instanciation RX ===
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uart_rx #(
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.CLK_FRE(CLK_FRE),
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.BAUD_RATE(UART_FRE)
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) uart_rx_inst (
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.clk (clk),
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.rst_p (rst),
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.rx_data (rx_data),
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.rx_data_valid (rx_data_valid),
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.rx_data_ready (rx_data_ready),
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.rx_pin (uart_rx)
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);
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// === Instanciation TX ===
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uart_tx #(
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.CLK_FRE(CLK_FRE),
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.BAUD_RATE(UART_FRE)
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) uart_tx_inst (
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.clk (clk),
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.rst_p (rst),
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.tx_data (tx_data),
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.tx_data_valid (tx_data_valid),
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.tx_data_ready (tx_data_ready),
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.tx_pin (uart_tx)
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);
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endmodule |