forked from tanchou/Verilog
145 lines
3.7 KiB
Verilog
145 lines
3.7 KiB
Verilog
module uart_rx #(
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parameter CLK_FREQ = 27_000_000,
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parameter BAUD_RATE = 115200
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)(
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input clk, //clock input
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input rst_p, //asynchronous reset input, high active
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input rx_enable, //data receiver module ready
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input rx_pin, //serial data input
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output reg[7:0] rx_data, //received serial data
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output reg rx_received //received serial data is valid
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);
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localparam CYCLE = CLK_FREQ / BAUD_RATE;
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//state machine code
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localparam S_IDLE = 1;
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localparam S_START = 2; //start bit
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localparam S_REC_BYTE = 3; //data bits
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localparam S_STOP = 4; //stop bit
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localparam S_DATA = 5;
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reg[2:0] state;
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reg[2:0] next_state;
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reg rx_d0; //delay 1 clock for rx_pin
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reg rx_d1; //delay 1 clock for rx_d0
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wire rx_negedge; //negedge of rx_pin
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reg[7:0] rx_bits; //temporary storage of received data
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reg[15:0] cycle_cnt; //baud counter
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reg[2:0] bit_cnt; //bit counter
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assign rx_negedge = rx_d1 && ~rx_d0; // Front déscendant
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always@(posedge clk or posedge rst_p) // Filtrage du signial
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begin
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if(rst_p == 1'b1)begin
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rx_d0 <= 1'b0;
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rx_d1 <= 1'b0;
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end else begin
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rx_d0 <= rx_pin;
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rx_d1 <= rx_d0;
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end
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end
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always@(posedge clk or posedge rst_p)begin // Compteur d'etat
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if(rst_p == 1'b1)
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state <= S_IDLE;
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else
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state <= next_state;
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end
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always@(*)begin
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case(state)
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S_IDLE:
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if(rx_negedge) // Detection du start bit
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next_state = S_START;
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else
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next_state = S_IDLE;
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S_START:
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if(cycle_cnt == CYCLE - 1) //one data cycle
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next_state = S_REC_BYTE;
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else
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next_state = S_START;
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S_REC_BYTE:
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data
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next_state = S_STOP;
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else
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next_state = S_REC_BYTE;
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S_STOP:
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if(cycle_cnt == CYCLE/2 - 1) //half bit cycle,to avoid missing the next byte receiver
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next_state = S_DATA;
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else
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next_state = S_STOP;
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S_DATA:
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if(rx_enable) //data receive complete
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next_state = S_IDLE;
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else
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next_state = S_DATA;
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default:
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next_state = S_IDLE;
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endcase
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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rx_received <= 1'b0;
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else if(state == S_STOP && next_state != state)
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rx_received <= 1'b1;
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else if(state == S_DATA && rx_enable)
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rx_received <= 1'b0;
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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rx_data <= 8'd0;
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else if(state == S_STOP && next_state != state)
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rx_data <= rx_bits;//latch received data
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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begin
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bit_cnt <= 3'd0;
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end
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else if(state == S_REC_BYTE)
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if(cycle_cnt == CYCLE - 1)
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bit_cnt <= bit_cnt + 3'd1;
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else
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bit_cnt <= bit_cnt;
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else
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bit_cnt <= 3'd0;
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end
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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cycle_cnt <= 16'd0;
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else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
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cycle_cnt <= 16'd0;
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else
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cycle_cnt <= cycle_cnt + 16'd1;
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end
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//receive serial data bit data
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always@(posedge clk or posedge rst_p)
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begin
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if(rst_p == 1'b1)
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rx_bits <= 8'd0;
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else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
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rx_bits[bit_cnt] <= rx_pin;
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else
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rx_bits <= rx_bits;
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end
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endmodule
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