forked from tanchou/Verilog
132 lines
3.5 KiB
Verilog
132 lines
3.5 KiB
Verilog
module uart_tx #(
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parameter CLK_FREQ = 27_000_000,
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parameter BAUD_RATE = 115200
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)(
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input wire clk,
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input wire rst_p,
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input wire[7:0] data,
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input wire tx_enable,
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output reg tx_ready,
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output wire tx
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);
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localparam CYCLE = CLK_FREQ / BAUD_RATE;
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localparam IDLE = 2'd0;
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localparam START = 2'd1;
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localparam DATA = 2'd2;
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localparam STOP = 2'd3;
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reg [1:0] state = IDLE;
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reg [1:0] next_state;
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reg [15:0] cycle_cnt; //baud counter
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reg tx_reg;
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reg [2:0] bit_cnt;
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reg [7:0] tx_data_latch = 0;
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assign tx = tx_reg;
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always@(posedge clk or posedge rst_p)begin // Avance d'etat
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if(rst_p == 1'b1)
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state <= IDLE;
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else
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state <= next_state;
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end
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always@(*) begin
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case(state)
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IDLE:
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if(tx_enable == 1'b1)
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next_state = START;
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else
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next_state = IDLE;
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START:
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if(cycle_cnt == CYCLE - 1)
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next_state = DATA;
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else
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next_state = START;
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DATA:
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if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7)
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next_state = STOP;
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else
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next_state = DATA;
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STOP:
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if(cycle_cnt == CYCLE - 1)
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next_state = IDLE;
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else
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next_state = STOP;
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default:
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next_state = IDLE;
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endcase
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end
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always@(posedge clk or posedge rst_p)begin // tx_ready block
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if(rst_p == 1'b1)
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tx_ready <= 1'b0; // Reset
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else if(state == IDLE && tx_enable == 1'b1)
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tx_ready <= 1'b0; // Pas prêt tant que les données sont valides
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else if(state == IDLE)
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tx_ready <= 1'b1;
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else if(state == STOP && cycle_cnt == CYCLE - 1)
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tx_ready <= 1'b1; // Prêt une fois le bit STOP envoyé
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else
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tx_ready <= tx_ready; // Reste inchangé dans d'autres cas
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end
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always@(posedge clk or posedge rst_p) begin // tx_data_latch block
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if(rst_p == 1'b1) begin
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tx_data_latch <= 8'd0;
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end else if(state == IDLE && tx_enable == 1'b1) begin
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tx_data_latch <= data; // Charger les données de data dans tx_data_latch
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end
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end
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always@(posedge clk or posedge rst_p)begin // DATA bit_cnt block
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if(rst_p == 1'b1)begin
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bit_cnt <= 3'd0;
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end else if(state == DATA)
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if(cycle_cnt == CYCLE - 1)
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bit_cnt <= bit_cnt + 3'd1;
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else
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bit_cnt <= bit_cnt;
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else
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bit_cnt <= 3'd0;
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end
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always@(posedge clk or posedge rst_p)begin // Cycle counter
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if(rst_p == 1'b1)
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cycle_cnt <= 16'd0;
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else if((state == DATA && cycle_cnt == CYCLE - 1) || next_state != state)
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cycle_cnt <= 16'd0;
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else
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cycle_cnt <= cycle_cnt + 16'd1;
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end
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always@(posedge clk or posedge rst_p)begin // tx state managment
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if(rst_p == 1'b1)
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tx_reg <= 1'b1;
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else
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case(state)
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IDLE,STOP:
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tx_reg <= 1'b1;
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START:
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tx_reg <= 1'b0;
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DATA:
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tx_reg <= tx_data_latch[bit_cnt]; // SENDING BYTE HERE
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default:
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tx_reg <= 1'b1;
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endcase
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end
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endmodule
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