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verlan
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Verilog_Louis
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436edae734ab0c5b4cb8dbdfdcc9d087c74b42ee
Verilog_Louis
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Semaine_4
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UART_FIFO
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scripts
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Gamenight77
1006b77e95
Update testbench and simulation scripts to use a unified output file name for GTKWave
2025-05-19 09:31:53 +02:00
..
build.bat
Loopback fifo fonctionne mais avec 3 valeur de décalage
2025-05-09 11:39:40 +02:00
clean.bat
Création de la structure du uart fifo
2025-05-06 09:42:26 +02:00
gtkwave.bat
Update testbench and simulation scripts to use a unified output file name for GTKWave
2025-05-19 09:31:53 +02:00
simulate.bat
Update testbench and simulation scripts to use a unified output file name for GTKWave
2025-05-19 09:31:53 +02:00