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Verilog_Louis
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4e16bb3cbeef1fa2fb37ef1a10a771d5b8c43356
Verilog_Louis
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Semaine_7
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Gamenight77
4e16bb3cbe
Fix timer conditions in DHT11 state machine for signal detection
2025-05-27 13:45:58 +02:00
..
DHT11
Refactor DHT11 interface to support 16-bit temperature and humidity data, update checksum handling, and improve state machine logic
2025-05-27 13:34:59 +02:00
DHT11_UART
Fix timer conditions in DHT11 state machine for signal detection
2025-05-27 13:45:58 +02:00
ESP32
Enhance DHT11 interface and update measurement delay in top module
2025-05-27 12:51:00 +02:00