forked from tanchou/Verilog
49 lines
1.3 KiB
Verilog
49 lines
1.3 KiB
Verilog
module fifo #(
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parameter SIZE = 16,
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parameter WIDTH = 8
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)(
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input wire clk,
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input wire wr_en,
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input wire[WIDTH-1:0] wr_data,
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input wire rd_en,
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output reg[WIDTH-1:0] rd_data,
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output wire full,
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output wire empty
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);
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localparam LOGSIZE = $clog2(SIZE);
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reg [WIDTH-1:0] fifo[0:SIZE-1];
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reg [LOGSIZE-1:0] wr_ptr;
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reg [LOGSIZE-1:0] rd_ptr;
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reg [LOGSIZE:0] count;
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assign full = (count == SIZE);
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assign empty = (count == 0);
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initial begin
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wr_ptr = 0;
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rd_ptr = 0;
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count = 0;
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end
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always @(posedge clk) begin // IN
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rd_data <= fifo[rd_ptr];
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if (wr_en && !full && rd_en && !empty) begin
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fifo[wr_ptr] <= wr_data;
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wr_ptr <= (wr_ptr == SIZE - 1) ? 0 : (wr_ptr + 1) ;
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rd_ptr <= (rd_ptr == SIZE - 1) ? 0 : (rd_ptr + 1) ;
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end else if (wr_en && !full) begin
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fifo[wr_ptr] <= wr_data;
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wr_ptr <= (wr_ptr == SIZE - 1) ? 0 : (wr_ptr + 1) ;
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count <= count + 1;
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end else if (rd_en && !empty) begin // OUT
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rd_ptr <= (rd_ptr == SIZE - 1) ? 0 : (rd_ptr + 1) ;
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count <= count - 1;
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end
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end
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endmodule
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