This website requires JavaScript.
Explore
Help
Sign In
verlan
/
Verilog_Louis
Watch
1
Star
0
Fork
0
You've already forked Verilog_Louis
forked from
tanchou/Verilog
Code
Pull Requests
Activity
Files
505f71974e0603cd13fe5f556c6d61f7168a0de3
Verilog_Louis
/
Semaine_2
/
Projet_esp32
History
Gamenight77
d8708d1bd5
Refactor ultrasonic FPGA module: replace sig_in with sig_ok for improved signal handling and update ESP32 command processing to support new client list command
2025-04-25 09:17:22 +02:00
..
esp32_code
Refactor ultrasonic FPGA module: replace sig_in with sig_ok for improved signal handling and update ESP32 command processing to support new client list command
2025-04-25 09:17:22 +02:00
Projet_esp32.md
Add README and project documentation for FPGA and ESP32 integration
2025-04-22 16:46:03 +02:00
protocole_esp_fpga.md
Enhance ESP32 command processing: add validation, error handling, and new command types for device management
2025-04-23 15:52:36 +02:00