forked from tanchou/Verilog
77 lines
1.8 KiB
Verilog
77 lines
1.8 KiB
Verilog
`timescale 1ns/1ps
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module tb_uart_tx;
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reg clk = 0;
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reg tx_enable = 0;
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reg [7:0] data_in = 8'h00;
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reg [7:0] data_out;
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wire tx;
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reg tx_ready;
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wire rx_recieved;
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always #18.5 clk = ~clk;
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other_uart_rx rx_instance(
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.clk(clk),
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.rx_pin(tx), // tx is connected to rx for testing
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.rst_n(1'b1),
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.rx_data(data_out),
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.rx_data_valid(rx_recieved),
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.rx_data_ready(1'b1)
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);
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uart_tx #(
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.CLK_FREQ(27_000_000),
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.BAUD_RATE(115_200)
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)tx_instance (
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.clk(clk),
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.tx_enable(tx_enable),
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.tx_ready(tx_ready),
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.data(data_in),
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.tx(tx),
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.rst_p(1'b0)
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);
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initial begin
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$dumpfile("runs/uart_tx.vcd");
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$dumpvars(0, tb_uart_tx);
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$display("======== Start UART TX test =========");
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#100;
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data_in <= 8'd234; // 234
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tx_enable <= 1;
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wait(tx_ready == 1'b0);
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tx_enable <= 0;
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// Attendre
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wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif
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$display("Data received: %d", data_out); // Afficher la valeur recu
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$display("Data expected: %d", data_in); // Afficher la valeur envoyee
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#1000;
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wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif
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data_in <= 8'd202; // 202
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tx_enable <= 1;
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wait(tx_ready == 1'b0);
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tx_enable <= 0;
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// Attendre
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wait (rx_recieved == 1'b1); // Attendre que le signal de reception soit actif
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$display("Data received: %d", data_out); // Afficher la valeur recu
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$display("Data expected: %d", data_in); // Afficher la valeur envoyee
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$display("======== END UART TX test =========");
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#1000;
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$stop;
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end
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endmodule |