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Verilog_Louis/Help/presentation_examples/led_walk/constraints/blink_led.cst
Gamenight77 f5e73d7379 struct
2025-05-02 15:51:18 +02:00

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IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clk" 4;
IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;