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Verilog_Louis/Semaine_4/UART_FIFO/tests
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Gamenight77 e124c7c0c4 Bloquer a cause du tx
2025-05-13 12:22:50 +02:00
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Python
Création de la structure du uart fifo
2025-05-06 09:42:26 +02:00
verilog
Bloquer a cause du tx
2025-05-13 12:22:50 +02:00