verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity
Files
6bb42700f8a951f8b3a1de05d0743800d0fbbf6e
Verilog_Louis/Help/presentation_examples/counter/project.bat
Gamenight77 f5e73d7379 struct
2025-05-02 15:51:18 +02:00

2 lines
76 B
Batchfile
Raw Blame History

@call c:\tools\oss-cad-suite\environment.bat
@tclsh scripts\project.tcl %*
View Git Blame Copy Permalink