This website requires JavaScript.
Explore
Help
Sign In
verlan
/
Verilog_Louis
Watch
1
Star
0
Fork
0
You've already forked Verilog_Louis
forked from
tanchou/Verilog
Code
Pull Requests
Activity
Files
790b85841b69af910c727bc8574250d702edea2a
Verilog_Louis
/
Semaine_4
History
Gamenight77
30bbe27510
ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer
2025-05-12 12:15:52 +02:00
..
FIFO
MAJ FIFO -> turn wire rd_data into register
2025-05-09 10:27:13 +02:00
UART
MAJ FIFO -> turn wire rd_data into register
2025-05-09 10:27:13 +02:00
UART_FIFO
Add README for UART loopback issue and delay explanation
2025-05-09 11:58:55 +02:00
UART_ULTRASON
ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer
2025-05-12 12:15:52 +02:00