forked from tanchou/Verilog
16 lines
244 B
Verilog
16 lines
244 B
Verilog
module counter (
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input wire clk,
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input wire rst,
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output reg [3:0] count
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);
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always @(posedge clk)
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begin
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if(rst)
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count <= 4'b0000;
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else
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count <= count + 1;
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end
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);
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endmodule |