forked from tanchou/Verilog
28 lines
469 B
Verilog
28 lines
469 B
Verilog
module top_module (
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input p1a, p1b, p1c, p1d, p1e, p1f,
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output p1y,
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input p2a, p2b, p2c, p2d,
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output p2y );
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wire tand1;
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wire tand2;
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wire and1;
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wire and2;
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wire or1;
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wire or2;
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assign tand1 = p1a & p1b & p1c;
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assign tand2 = p1d & p1e & p1f;
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assign and1 = p2a & p2b;
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assign and2 = p2c & p2d;
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assign or1 = tand1 | tand2;
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assign or2 = and1 | and2;
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assign p1y = or1;
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assign p2y = or2;
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endmodule |