forked from tanchou/Verilog
97 lines
2.8 KiB
Python
97 lines
2.8 KiB
Python
import cocotb
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from cocotb.triggers import Timer, RisingEdge, First
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# from cocotb.triggers import FallingEdge, RisingEdge, First, Timer, Event
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from cocotb_test.simulator import run
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import pytest
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import os
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async def generate_clock(dut):
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"""Generate clock pulses."""
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# for cycle in range(100):
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while True:
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dut.clk.value = 0
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await Timer(5, "ns")
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dut.clk.value = 1
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await Timer(5, "ns")
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@cocotb.test()
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async def counter_simple_test(dut):
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await cocotb.start(generate_clock(dut)) # run the clock "in the background"
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#dut._log.info("my_signal_1 is %s", dut.my_signal_1.value)
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# await Timer(10000, units='ns')
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#for i in range(dut.WRITE_NB.value):
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# await RisingEdge(dut.write_transaction)
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#for i in range(dut.READ_NB.value):
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# await RisingEdge(dut.read_transaction)
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#await Timer(400, units="ns")
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await RisingEdge(dut.clk)
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dut.reset.value = 1
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await RisingEdge(dut.clk)
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dut.reset.value = 0
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dut.en.value = 1
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await Timer(400, units="ns")
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await RisingEdge(dut.clk)
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dut.en.value = 0
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await Timer(50, units="ns")
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await RisingEdge(dut.clk)
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dut.en.value = 1
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await Timer(500, units="ns")
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# assert strobe : have a new process counting strobes
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def test_counter_runner():
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current_dir = os.path.dirname(__file__)
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root = "{current_dir}../.."
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print(f"root: {root}")
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run(
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# python_search=[os.path.join(current_dir, "../cocotb/")],
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python_search=[current_dir],
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verilog_sources=[
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f"{root}/src/verilog/counter.v",
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], # sources
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toplevel="counter", # top level HDL
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module="counter_test", # name of cocotb test module
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sim_build=f"{root}/runs/cocotb", # + "_".join(("{}={}".format(*i) for i in parameters.items())),
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# parameters = parameters,
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waves=1,
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)
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@pytest.mark.skipif(os.getenv("SIM") == "verilator", reason="Custom for verilator")
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@pytest.mark.parametrize("parameters", [{"WIDTH": 4, "INITIAL_VALUE": 5}, {"WIDTH": 8, "INITIAL_VALUE": 15}, {"WIDTH": 8, "INITIAL_VALUE": 255}])
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def test_parametrized_counter_runner(parameters):
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current_dir = os.path.dirname(__file__)
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#from pathlib import Path
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#proj_path = Path(__file__).resolve().parent
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root = "{current_dir}../.."
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run(
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# python_search=[os.path.join(current_dir, "../cocotb/")],
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python_search=[current_dir],
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verilog_sources=[
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f"{root}/src/verilog/counter.v",
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], # sources
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toplevel="counter", # top level HDL
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module="counter_test", # name of cocotb test module
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sim_build=f"{root}/runs/cocotb/" + "_".join(("{}={}".format(*i) for i in parameters.items())),
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parameters = parameters,
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waves=1,
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)
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if __name__ == "__main__":
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test_counter_runner()
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