forked from tanchou/Verilog
55f9161dfa
- Implemented the uart_tx module for UART transmission with configurable clock frequency and baud rate. - Added a testbench (uart_tx_tb) to verify the functionality of the uart_tx module, including signal generation for start, data, and clock. - Created a backup of the previous testbench (uart_tx_tb_old) for reference.
34 lines
710 B
Verilog
34 lines
710 B
Verilog
module top_uart_rx_tx(
|
|
input wire clk,
|
|
input wire start, // Commencer l'ecriture
|
|
input wire [7:0] data_in,
|
|
input wire rx,
|
|
output wire [7:0] data_out,
|
|
output wire valid, // Si 1 alors on peut lire
|
|
output wire tx
|
|
);
|
|
|
|
parameter CLK_FREQ = 27_000_000;
|
|
parameter BAUD_RATE = 115_200;
|
|
|
|
uart_tx #(
|
|
.CLK_FREQ(CLK_FREQ),
|
|
.BAUD_RATE(BAUD_RATE)
|
|
) tx_instance (
|
|
.clk(clk),
|
|
.start(start),
|
|
.data(data_in),
|
|
.tx(tx)
|
|
);
|
|
|
|
uart_rx #(
|
|
.CLK_FREQ(CLK_FREQ),
|
|
.BAUD_RATE(BAUD_RATE)
|
|
) rx_instance (
|
|
.clk(clk),
|
|
.rx(rx),
|
|
.data(data_out),
|
|
.valid(valid)
|
|
);
|
|
|
|
endmodule |