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Verilog_Louis
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92144d315eb0061da6e4ce27d1a180372a241a39
Verilog_Louis
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Semaine_2
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Projet_esp32
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esp32_code
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Projet_code
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Gamenight77
d8708d1bd5
Refactor ultrasonic FPGA module: replace sig_in with sig_ok for improved signal handling and update ESP32 command processing to support new client list command
2025-04-25 09:17:22 +02:00
..
ESP32
Refactor ultrasonic FPGA module: replace sig_in with sig_ok for improved signal handling and update ESP32 command processing to support new client list command
2025-04-25 09:17:22 +02:00
esp32_read.py
Refactor ESP32 communication: update packet structure, enhance frame reading, and implement command interpretation
2025-04-24 10:43:25 +02:00
read_trame_test.py
Refactor ESP32 communication: update packet structure, enhance frame reading, and implement command interpretation
2025-04-24 10:43:25 +02:00
test_command.py
Refactor ultrasonic FPGA module: replace sig_in with sig_ok for improved signal handling and update ESP32 command processing to support new client list command
2025-04-25 09:17:22 +02:00