forked from tanchou/Verilog
Louis TANCHOU
54bf6df85b
- Implemented a FIFO buffer in Verilog for data storage. - Created a simplified UART transmitter (txuartlite) for serial communication. - Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow. - Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission. - Added a testbench (tb_dht11) for simulating the DHT11 module functionality. - Updated README with project description and command references. - Created build and simulation scripts for both Linux and Windows environments. - Added constraints file for hardware configuration. - Implemented a state machine for managing measurement and data transmission.
9 lines
256 B
Batchfile
9 lines
256 B
Batchfile
@call c:\oss-cad-suite\environment.bat
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@echo off
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mkdir runs
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if "%1"=="sim" call scripts\windows\simulate.bat
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if "%1"=="wave" call scripts\windows\gtkwave.bat
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if "%1"=="clean" call scripts\windows\clean.bat
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if "%1"=="build" call scripts\windows\build.bat |