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verlan
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Verilog_Louis
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a792f85adf274a76a5936b033774f6c325d1be06
Verilog_Louis
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Semaine_4
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Gamenight77
a792f85adf
loopback fonctionne avec le rxuartlite
2025-05-09 09:15:28 +02:00
..
FIFO
Tb for fifo working fine
2025-05-06 09:14:59 +02:00
UART
loopback fonctionne avec le rxuartlite
2025-05-09 09:15:28 +02:00
UART_FIFO
Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality
2025-05-07 09:46:43 +02:00
UART_ULTRASON
Add WAIT state to FSM and implement delay mechanism in UART module
2025-05-07 18:07:45 +02:00