forked from tanchou/Verilog
92 lines
2.4 KiB
Verilog
92 lines
2.4 KiB
Verilog
module uart_top(
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input wire clk,
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input wire rst,
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input wire uart_rx,
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output wire uart_tx,
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// Interfaces RX
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output wire [7:0] rx_data,
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output wire rx_data_valid,
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input wire rx_data_ready,
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input wire read_fifo,
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// Interfaces TX
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input wire [7:0] tx_data,
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input wire tx_data_valid,
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output wire tx_data_ready
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);
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parameter CLK_FRE = 27_000_000; // Hz
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parameter BAUD_RATE = 115200; // Baudrate
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// === Signaux internes ===
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wire [7:0] uart_rx_data;
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wire uart_rx_data_valid;
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wire uart_rx_data_ready;
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wire [7:0] uart_tx_data;
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wire uart_tx_data_valid;
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wire uart_tx_data_ready;
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wire tx_fifo_empty;
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wire tx_fifo_full;
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wire rx_fifo_empty;
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wire rx_fifo_full;
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// === FIFO RX ===
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rx_fifo #(
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.WIDTH(8),
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.DEPTH(16)
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) rx_fifo_inst (
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.clk (clk),
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.rst_p (rst),
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.rx_data_in (uart_rx_data),
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.rx_data_valid (uart_rx_data_valid),
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.rx_data_out (rx_data),
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.rx_data_ready (rx_data_ready),
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.fifo_empty (rx_fifo_empty),
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.fifo_full (rx_fifo_full),
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.read_fifo (read_fifo)
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);
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// === FIFO TX ===
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tx_fifo #(
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.WIDTH(8),
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.DEPTH(16)
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) tx_fifo_inst (
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.clk (clk),
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.rst_p (rst),
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.tx_data_in (tx_data),
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.tx_data_valid (tx_data_valid),
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.tx_data_ready (tx_data_ready),
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.tx_data_out (uart_tx_data),
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.uart_tx_ready (uart_tx_data_ready),
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.fifo_empty (tx_fifo_empty),
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.fifo_full (tx_fifo_full)
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);
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// === Instanciation RX UART ===
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uart_rx uart_rx_inst (
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.clk (clk),
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.rst_p (rst),
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.rx_data (uart_rx_data),
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.rx_data_valid (uart_rx_data_valid),
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.rx_data_ready (uart_rx_data_ready),
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.rx_pin (uart_rx)
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);
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// === Instanciation TX UART ===
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uart_tx uart_tx_inst (
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.clk (clk),
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.rst_p (rst),
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.data (uart_tx_data),
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.tx_data_valid (uart_tx_data_valid),
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.tx_data_ready (uart_tx_data_ready),
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.tx (uart_tx)
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);
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assign uart_tx_data_valid = (!tx_fifo_empty && uart_tx_data_ready) ? 1'b1 : 1'b0;
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endmodule
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