Gamenight77 abef18227c Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality

2025-05-07 09:46:43 +02:00

..

constraints

Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality

2025-05-07 09:46:43 +02:00

IP/verilog

rx fifo et tx fifo on l'air de fonctionner lors des testbenchs

2025-05-06 10:59:08 +02:00

scripts

Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality

2025-05-07 09:46:43 +02:00

src/verilog

Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality

2025-05-07 09:46:43 +02:00

tests

rx fifo et tx fifo on l'air de fonctionner lors des testbenchs

2025-05-06 10:59:08 +02:00

.gitignore

Création de la structure du uart fifo

2025-05-06 09:42:26 +02:00

project.bat

Création de la structure du uart fifo

2025-05-06 09:42:26 +02:00