forked from tanchou/Verilog
72 lines
2.4 KiB
Verilog
72 lines
2.4 KiB
Verilog
module uart_rx (
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input wire clk,
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input wire rx, // signal reçues
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output reg [7:0] data, // Données decoder
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output reg valid = 0, // Indicateur de données valides
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output reg ready = 1 // Indicateur de réception prête
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);
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parameter CLK_FREQ = 27_000_000;
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parameter BAUD_RATE = 115_200;
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localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
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localparam IDLE = 2'b00;
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localparam START = 2'b01;
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localparam DATA = 2'b10;
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localparam STOP = 2'b11;
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reg [1:0] state = IDLE;
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reg [3:0] bit_index;
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reg [15:0] clk_count;
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reg [7:0] rx_data = 0;
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always @(posedge clk) begin
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case (state)
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IDLE: begin
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ready <= 1;
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if (!rx) begin // start bit (0)
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state <= START;
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clk_count <= 0;
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bit_index <= 0;
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valid <= 0;
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ready <= 0;
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end
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end
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START: begin
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if (clk_count < (BIT_PERIOD / 2) - 1) begin // Attendre juste 0.5 bit
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clk_count <= clk_count + 1;
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end else begin
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clk_count <= 0;
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state <= DATA;
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end
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end
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DATA: begin
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if (clk_count < BIT_PERIOD - 1) begin
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clk_count <= clk_count + 1;
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end else begin
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clk_count <= 0;
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rx_data[bit_index] <= rx; // Recevoir les données (8 bits)
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bit_index <= bit_index + 1;
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if (bit_index == 7) begin
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state <= STOP; // Passer à l'état d'arrêt
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end
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end
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end
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STOP: begin
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if (clk_count < BIT_PERIOD - 1) begin
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clk_count <= clk_count + 1;
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end else begin
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state <= IDLE;
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data <= rx_data;
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valid <= 1;
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ready <= 1;
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end
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end
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endcase
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end
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endmodule |