forked from tanchou/Verilog
57 lines
1.9 KiB
Verilog
57 lines
1.9 KiB
Verilog
module uart_tx(
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input wire clk,
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input wire start, // Signal de démarrage de la transmission
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input wire [7:0] data, // Données à transmettre
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output reg tx, // Sortie de transmission
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output reg busy // Indicateur de transmission en cours
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);
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parameter CLK_FREQ = 27_000_000;
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parameter BAUD_RATE = 115_200;
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localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
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reg [3:0] bit_index;
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reg [15:0] clk_count;
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reg [7:0] tx_data = 0;
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initial begin
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tx = 1; // État idle (1)
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busy = 0; // Pas de transmission en cours
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end
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always @(posedge clk) begin
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if (start && !busy) begin
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busy <= 1; // Démarrer la transmission
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bit_index <= 0; // Réinitialiser l'index du bit
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clk_count <= 0; // Réinitialiser le compteur d'horloge
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tx_data <= data;
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tx <= 1; // État idle (1)
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end else if (busy) begin
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if (clk_count < BIT_PERIOD - 1) begin
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clk_count <= clk_count + 1;
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end else begin
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clk_count <= 0;
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if (bit_index == 0) begin
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tx <= 0; // Start bit (0)
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end else if (bit_index < 9) begin
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tx <= tx_data[bit_index - 1]; // Transmettre les données (8 bits)
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end else if (bit_index == 9) begin
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tx <= 1; // Stop bit (1)
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end else begin
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busy <= 0; // Fin de la transmission
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end
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bit_index <= bit_index + 1; // Passer au bit suivant
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end
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end else begin
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tx <= 1; // État idle (1)
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end
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end
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endmodule |