forked from tanchou/Verilog
65 lines
1.3 KiB
Verilog
65 lines
1.3 KiB
Verilog
`timescale 1ns / 1ps
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module tb_uart_rx;
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reg clk = 0;
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reg rx = 1;
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wire [7:0] data;
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wire valid;
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wire ready;
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localparam CLK_FREQ = 27_000_000;
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localparam BAUD_RATE = 115_200;
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localparam BIT_PERIOD = CLK_FREQ / BAUD_RATE;
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localparam CLK_PERIOD_NS = 1000000000 / CLK_FREQ;
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uart_rx #(
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.CLK_FREQ(CLK_FREQ),
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.BAUD_RATE(BAUD_RATE)
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) rx_instance (
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.clk(clk),
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.rx(rx),
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.data(data),
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.valid(valid),
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.ready(ready)
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);
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always #(CLK_PERIOD_NS/2) clk = ~clk;
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task send_bit(input reg b);
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begin
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rx <= b;
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#(BIT_PERIOD * CLK_PERIOD_NS);
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end
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endtask
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integer i;
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task send_byte(input [7:0] byte);
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begin
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send_bit(0);
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for (i = 0; i < 8; i = i + 1)
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send_bit(byte[i]);
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send_bit(1);
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#(BIT_PERIOD * CLK_PERIOD_NS);
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end
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endtask
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initial begin
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$display("Start UART RX test");
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#100;
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send_byte(8'b01010101);
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#(10 * BIT_PERIOD * CLK_PERIOD_NS);
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if (valid && data == 8'b01010101)
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$display("Test ok : data = %b", data);
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else
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$display("Test pas ok : data = %b, valid = %b", data, valid);
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$finish;
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end
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endmodule
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