forked from tanchou/Verilog
49 lines
780 B
Verilog
49 lines
780 B
Verilog
`timescale 1ns/1ps
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module tb_uart_tx;
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reg clk = 0;
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reg start = 0;
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reg [7:0] data = 8'h00;
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wire tx;
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wire busy;
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always #18.5 clk = ~clk;
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uart_tx #(
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.CLK_FREQ(27_000_000),
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.BAUD_RATE(115_200)
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)tx_instance (
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.clk(clk),
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.start(start),
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.data(data),
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.tx(tx),
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.busy(busy)
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);
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initial begin
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$dumpfile("uart_tx.vcd");
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$dumpvars(0, tb_uart_tx);
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#100;
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data <= 8'hA5; // 10100101 0xA5
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start <= 1;
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#37 start <= 0;
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// Attendre
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wait (busy == 0);
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#1000;
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data <= 8'h3C; // 00111100 0x3C
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start <= 1;
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#37 start <= 0;
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wait (busy == 0);
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#1000;
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$stop;
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end
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endmodule |