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Verilog_Louis/Semaine 1/Capteur_recule_avec_deux_broche
Gamenight77 6dfd8768a0 Add testbench for top_ultrasonic_led module
- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the functionality of the `top_ultrasonic_led` module.
- Included necessary signal definitions and event triggers for clock, reset, start, echo, and trigger signals.
- Implemented a state machine to handle the ultrasonic measurement process and LED display logic.
- Added simulation parameters for distance measurement and LED control.
- Integrated VPI calls for waveform dumping and simulation control.
2025-04-16 14:58:04 +02:00
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