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Verilog_Louis
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e086ba8ef0d87887fe9a3cc31c8162260de993b1
Verilog_Louis
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Semaine_2
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Projet_esp32
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esp32_code
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Gamenight77
d8708d1bd5
Refactor ultrasonic FPGA module: replace sig_in with sig_ok for improved signal handling and update ESP32 command processing to support new client list command
2025-04-25 09:17:22 +02:00
..
blink_led_test
Add WiFi access point functionality and client management to ESP32 code
2025-04-23 10:22:02 +02:00
Projet_code
Refactor ultrasonic FPGA module: replace sig_in with sig_ok for improved signal handling and update ESP32 command processing to support new client list command
2025-04-25 09:17:22 +02:00
Wifi_ap
Add WiFi access point functionality and client management to ESP32 code
2025-04-23 10:22:02 +02:00