forked from tanchou/Verilog
84 lines
1.9 KiB
Verilog
84 lines
1.9 KiB
Verilog
module top_uart_loopback (
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input wire clk, // 27 MHz
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input wire rx,
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output wire tx,
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output reg [5:0] leds
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);
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wire rx_received;
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wire [7:0] rx_data;
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reg [7:0] tx_data;
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reg tx_enable;
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wire tx_ready;
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initial begin
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leds = 6'b111111;
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end
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// === UART RX ===
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rxuartlite uart_rx_inst (
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.i_clk(clk),
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.i_reset(1'b0),
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.i_uart_rx(rx),
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.o_wr(rx_received),
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.o_data(rx_data)
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);
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// === UART TX ===
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uart_tx uart_tx_inst (
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.clk(clk),
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.rst_p(1'b0),
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.data(data_const),
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.tx_enable(tx_enable),
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.tx_ready(tx_ready),
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.tx(tx)
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);
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// === FSM avec délai ===
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localparam IDLE = 0, WAIT = 1, SEND = 2;
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reg [1:0] state = IDLE;
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reg [8:0] delay_counter = 0;
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always @(posedge clk) begin
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leds[5] <= rx;
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leds[4] <= tx;
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case (state)
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IDLE: begin
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tx_enable <= 0;
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delay_counter <= 0;
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if (rx_received && tx_ready) begin
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tx_data <= 8'h31; // Valeur à envoyer
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state <= WAIT;
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leds[0] <= 0;
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leds[1] <= 1;
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end
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end
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WAIT: begin
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if (tx_ready) begin
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tx_enable <= 1;
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state <= SEND;
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end else begin
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tx_enable <= 0;
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end
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end
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SEND: begin
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if (!tx_ready) begin // Attendre que la transmission commence
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tx_enable <= 0;
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end else if (tx_ready && tx_enable == 0) begin
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state <= IDLE; // Transmission terminée, retour à l’attente
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end
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leds[0] <= 0;
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leds[1] <= 0;
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end
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endcase
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end
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endmodule |