forked from tanchou/Verilog
12 lines
271 B
Verilog
12 lines
271 B
Verilog
module top_module(
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input [3:0] in,
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output out_and,
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output out_or,
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output out_xor
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);
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assign out_and = in[0] & in[1] & in[2] & in[3];
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assign out_or = in[0] | in[1] | in[2] | in[3];
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assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3];
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endmodule |