forked from tanchou/Verilog
37 lines
418 B
Verilog
37 lines
418 B
Verilog
`timescale 1ns/1ps
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`default_nettype none
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module blink_tb ();
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reg clk = 0;
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initial forever #5 clk = !clk;
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wire led;
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blink #(.CLK_SPEED(20)) bl (.clk(clk),.led(led));
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initial begin
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`ifdef VCD_DUMP
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$dumpfile("blink_tb.vcd");
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$dumpvars(0,blink_tb);
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`endif
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end
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initial begin
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`ifdef END_TIME
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#`END_TIME $finish();
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`else
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#1000 $finish();
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`endif
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end
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initial begin
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#500 $finish();
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end
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endmodule |