forked from tanchou/Verilog
34 lines
544 B
Verilog
34 lines
544 B
Verilog
`timescale 1ns/1ps
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`default_nettype none
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module blink #(
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parameter CLK_SPEED = 27_000_000
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)
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(
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input wire clk,
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output reg led
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);
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wire strobe;
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localparam ONE_HALF_S = CLK_SPEED / 2;
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localparam ONE_S = CLK_SPEED ;
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localparam TWO_S = CLK_SPEED *2;
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localparam TIME = TWO_S;
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localparam TIME_WIDTH = $clog2(TIME);
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initial led = 0;
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counter #(.WIDTH(TIME_WIDTH), .INITIAL_VALUE(TIME)) counter_inst
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(
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.clk(clk),
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.reset(1'b0),
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.en(1'b1),
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.strobe(strobe)
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);
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always_ff @(posedge clk)
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if(strobe) led <= !led;
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endmodule |