forked from tanchou/Verilog
49 lines
726 B
Verilog
49 lines
726 B
Verilog
`timescale 1ns/1ps
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`default_nettype none
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module counter_tb ();
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reg clk = 0;
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initial forever #5 clk = !clk;
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wire strobe;
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reg reset = 1'b0;
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reg en = 1'b1;
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counter #(.WIDTH(8),.INITIAL_VALUE(15)) count (.clk(clk),.en(en), .reset(reset), .strobe(strobe));
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initial begin
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`ifdef VCD_DUMP
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$dumpfile("counter_tb.vcd");
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$dumpvars(0,counter_tb);
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`endif
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end
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initial begin
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`ifdef END_TIME
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#`END_TIME $finish();
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`else
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#1000 $finish();
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`endif
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end
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initial begin
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@(posedge clk) reset = 1;
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@(posedge clk) reset = 0;
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en = 1;
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#400;
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@(posedge clk) en = 0;
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#50;
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@(posedge clk) en = 1;
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#500 $finish();
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end
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always @(posedge clk) begin
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if (strobe) $display("Strobe");
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end
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endmodule |