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Verilog_Louis/Semaine_4/UART_FIFO/project.bat

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2025-05-06 09:42:26 +02:00
@call c:\oss-cad-suite\environment.bat
@echo off
if "%1"=="sim" call scripts\simulate.bat
if "%1"=="wave" call scripts\gtkwave.bat
if "%1"=="clean" call scripts\clean.bat
if "%1"=="build" call scripts\build.bat